This application relates to designs for cell based arrays, and particularly relates to low power, high density designs for cell based arrays.
The use of gate arrays and standard cells has become well known as an effective and efficient method for rapidly developing new semiconductor products of substantial complexity. Such standard cells are typically used in cell-based arrays, and have wide application within the industry. A widely-accepted design for a gate array architecture that provides standard cell type densities is based on the design described in U.S. Pat. No. 5,289,021, commonly assigned to the assignee of the present invention and incorporated herein by reference.
However, despite the many advantages offered by cell based arrays, prior art designs cells have suffered from some limitations which have become more apparent as line widths have been reduced and complexity has increased. In particular, the typical prior art standard cell has been limited to a relatively low ratio between compute and drive cells. More specifically, prior art designs have limited the ratio between compute and drive cells to no more than three- or four-to-one. Moreover, manufacturing limitations have served to impose a fixed, three-to-one limitation on most if not all prior art designs. Although the three-to-one ratio has enabled efficient construction of a great many circuits, and is particularly well suited to many high performance designs, there remain other applicationsxe2x80x94for example, low power applicationsxe2x80x94which could benefit from a ratio of compute to drive cells other than (and typically greater than) three-to-one.
In addition, the nature of the compute and drive cell paradigm typically involves the use of only two types of cells to achieve all intended functions. While this has been and will continue to be very successful for a great many designs, demands for increasing density and lower power consumption make desirable cell designs which can meet these increasingly difficult objectives.
As a result, there has been a need to develop a cell based array design which permits the implementation of high density, lower power designs which use more efficiently the available die area.
The present invention substantially overcomes the limitations of the prior art by providing a highly flexible, heterogeneous architecture for portable, high density standard cell and gate array applications. More specifically, the present invention provides a trio of dense and flexible building blocks for improved implementation of logic cells. The building blocks comprise specialized cells which are sizeable and yet tailored to the particular functions they will likely be asked to perform. By combining the flexibility offered by the plurality of cell types, density can be better optimized while at the same time offering either higher performance or lower power operation.
The present invention achieves the foregoing objectives by providing three different types of cells (and their derivatives) for performing specialized functions, referred to sometimes hereinafter as transmission gate (T), logic (L) and drive (D) cells and, in the aggregate, as TLD cells. Each of the three types of cells are made through compilation via leaf cells; a wide range of transistor sizing is possible through leaf cells and via software.
The trio of TLD cells can be arranged in a predetermined array format for use as a gate array. For standard cell solutions, the arrangement of the building blocks can be optimized freely to suit each target logic gate.
The transmission gate (T) cell of the present invention typically comprises two pair of small, sizeable, CMOS transistors and is intended for mux implementation using CMOS transmission gates or other areas where small devices are required, such as SRAM. Gate connections are typically made through poly-switch-box (PSB) cells. For the sake of avoiding overcomplication, only exemplary forms of T cells will be discussed hereinafter, although it will be apparent to those skilled in the art that various derivatives of the T cell are possible with various styles of abutment.
Logic or L cells, like T cells, are typically comprised of two medium sized, sizeable CMOS transistor pairs. L cells are typically used for general CMOS logic implementation. As with T cells, gate connections are typically made through PSB cells, and various derivatives are included within the scope of the invention including different styles of abutment.
Drive or D cells are typically intended for maximum drive capability, and so comprise larger transistors than either T or L cells. An exemplary D cell comprises two larger, sizeable CMOS transistor pairs. As with the other types of cells, various derivative forms also exist, including various styles of abutment. As noted previously, each type of cell can be created by cell compilation using leaf cells. In addition, each type of cell can be configured with either a straight gate design or a bent gate design. Bent gate designs typically offer greater densities that straight gate designs. In addition, two abutting T cells or L cells can either share the active area (i.e., gate isolated) or can be separated by field isolation.
In accordance with the present invention, the TLD cells can be configured in what may be thought of as four different families of designs. The TLD cells may be combined in a columnar style in either the straight gate or the bent gate version. Alternatively, the TLD cells may be combined in a row style in either the straight gate or the bent gate version. In the columnar style, the T and L cells are typically stacked, and one or more TL pairs are typically arrayed with a D cell. In the row style, the T and L cells are placed laterally adjacent, and again one or more TL pairs may be arrayed with a D cell. The small capacitance of the T cell can be seen to provide improved power and performance over earlier designs, while the larger drive transistors of the D cell of the present invention permits improved drive capability.
The foregoing and other advantages of the present invention may be better appreciated from the following Detailed Description of the Invention, taken together with the attached Figures.